The present invention relates to a nonvolatile semiconductor memory device enabling high-speed erase where a low threshold is used as an erased state, and to a method of detecting an overerased cell in the nonvolatile semiconductor memory device.
Conventionally, ETOX (EPROM Thin Oxide: brand name of an Intel product) is used as the most commonly used flash memory. FIG. 12 is a schematic cross sectional view showing this ETOX-type flash memory cell. As shown in FIG. 12, a floating gate 5 is formed on a source 1, a drain 2 and a substrate (well) 3 between the source and the drain via a tunnel oxide film 4. A control gate 7 is formed on the floating gate 5 via an interlayer insulating film 6.
The operation principle of the ETOX-type flash memory will be explained below. As shown in Table 1, at the time of write, a voltage Vpp (for example, 10 V) is applied to the control gate 7, a reference voltage Vss (for example, 0 V) is applied to the source 1, and a voltage of 6 V is applied to the drain 2. Consequently, a large amount of current is allowed to flow in a channel layer, hot electrons are generated in a portion on the drain 2 side where an electric field is high, and electrons are implanted into the floating gate 5. As a result, a threshold voltage rises, and data is written to the memory cell. FIG. 13 shows threshold voltage distributions in a written state and an erased state. As shown in FIG. 13, the threshold voltage of a written memory cell is 5 V or higher. It is noted that open of the drain 2 in Table 1 means a voltage applied to the drain 2 of a memory cell to which data is not to be written.
Furthermore, at the time of erase, a voltage Vnn (for example, xe2x88x929 V) is applied to the control gate 7, a voltage Vpe (for example, 6 V) is applied to the source 1, and the drain 2 is made open to pull electrons from the floating gate 5 to the source 1 side and lower the threshold voltage. As a result, the threshold voltage of an erased memory cell becomes 1.5-3 V as shown in FIG. 13.
At the time of read, a voltage of 1 V is applied to the drain 2 and a voltage of 5 V is applied to the control gate 7. Then, when the memory cell is in an erased state, that is, when the threshold voltage is low, a current is allowed to flow into the cell and its state is determined as xe2x80x9c1xe2x80x9d. On the other hand, when the threshold voltage is high and the memory cell is in a written state, a current is not allowed to flow into the cell and its state is determined as xe2x80x9c0xe2x80x9d.
According to such an operation principle as the above, write, erase and read operations are performed. At the time of erase in an actual device, processing is performed in units of relatively large blocks of 64 kB for example. Meanwhile, some memory cells in a block where the erase processing is performed have a threshold voltage in a program state (high voltage) and others have a threshold voltage in an erased state (low voltage). That is, memory cells having two kinds of threshold voltages shown in FIG. 13 are mixed.
In this case, when an erase pulse is further added to memory cells in an erased state, the threshold voltages of the memory cells already in an erased state become in an excessively erased (overerased) state. Also, when there are memory cells whose threshold voltages decrease more rapidly than those of other memory cells due to variation in erase characteristic, the threshold voltages of the memory cells whose threshold voltages decreases more rapidly than others become in an overerased state. This is particularly problematic when the overerased state progresses, resulting in a negative threshold voltage.
In general, 0 V is applied to control gates of unselected memory cells at the time of read, write-verify or erase-verify. However, when a memory cell having a negative threshold voltage exists among the unselected memory cells, a cell current is allowed to flow into this memory cell although the memory cell is not selected. Therefore, when a selected memory cell M00 and an overerased cell M (1023, 0) are connected to the same bit line BL0 as shown in FIG. 14, a cell current flowing into the unselected overerased cell M (1023, 0) is added to the cell current flowing into the selected memory cell M00. Thus, the cell current measured in the bit line BL0 has a large value. Therefore, the threshold voltage of a program cell is apparently determined as low (an erased state). Thus, when a memory cell having a negative threshold voltage exists, an operation cannot be performed precisely at the time of the read, write-verify or erase-verify, and, as a result, a normal device operation cannot be performed.
In order to prevent such a problem, a complicated erase algorithm is used at the time of erase so that no memory cell having a negative threshold voltage exists. FIG. 3 shows the fundamental algorithm.
In FIG. 3, when an erase operation is started, first, a program before erase is performed for all memory cells in step S1. The voltage applied at this time is the same as that of the write operation described above.
In step S2, verify of the program before erase is performed. Detail description thereof is not given here, however, as a result of the verify of the program before erase, if there exists even one memory cell whose threshold voltage does not reach a predetermined voltage (5.0 V or higher in FIG. 13) because the program state is insufficient, the program is performed for the memory cell again, and the program and the verify are repeated until the threshold voltage of the memory cell becomes the predetermined voltage (5.0 V) or higher. Then, when the threshold voltage of the memory cell becomes the predetermined voltage (5.0 V) or higher, the program proceeds to the address of the next memory cell. Thus, when threshold voltages of all memory cells become the predetermined voltage or higher, the verify of the program before erase is terminated.
In step S3, an erase pulse is applied. This erase pulse application processing is performed in a unit of blocks. That is, data is erased in all memory cells in a block at the same time by making the drain 2 open to apply xe2x88x929 V to the control gate 7 and 6 V to the source 1.
In step S4, when the erase pulse application is terminated as described above, erase-verify is performed to determine whether all memory cells in the block have a predetermined threshold voltage or lower (3 V or lower in this case). Detail description is not given here, but, when a memory cell whose threshold voltage is not the predetermined voltage or lower is found, erase-verify is once stopped, and an erase pulse is applied again. This operation is repeated until threshold voltages of all memory cells become the predetermined voltage or lower.
In step S5, overerased cell detection and a soft program described in detail later are performed. Then, the erase operation is terminated.
FIG. 15 shows a general algorithm of the overerased cell detection performed in step S5 in the flow chart of the erase operation shown in FIG. 3. Hereafter, operations in the overerased cell detection and the software program will be explained in reference to a flow chart shown in FIG. 15 and array configuration of a flash memory shown in FIG. 2. In FIG. 2, the flash memory cell array is configured by memory cells M arranged in a matrix, word lines WL connected to control gates of the memory cells M arranged in the line direction, bit lines BL connected to drains of the memory cells M arranged in the column direction and a common source line SL for connecting sources of all the memory cells M00 to M (1023, 511) constituting a block.
In FIG. 15, an initial value xe2x80x9c0xe2x80x9d is set in a column address CA (=bit line BL number) in step S11. In step S12, an initial value xe2x80x9c0xe2x80x9d is set in a row address RA (=word line WL number). In step S13, a threshold voltage Vt of a memory cell M (RA, CA) is verified, the memory cell M (RA, CA) being positioned at an intersection of the row address RA and the column address CA. In step S14, as a result of this verification, it is judged whether the threshold voltage Vt of the memory cell M (RA, CA) is higher than 0.5 V. As a result, when the threshold voltage is higher than 0.5 V, it is determined that the memory cell M (RA, CA) is not in an overerased state, and processing proceeds to step S15. On the other hand, when the threshold voltage is 0.5 V or lower, it is determined that the memory cell M (RA, CA) is in an overerased state (verify is performed), and processing proceeds to step S19.
In step S15, the row address RA is incremented. As a result, when word line WL0 is selected in step S12, word line WL1 is selected. In step S16, it is judged whether the row address RA is final address RAMAX (=1024) or higher. As a result, when the row address is the final address RAMAX or higher, processing proceeds to step 17, and, when the row address is lower than the final address RAMAX, processing returns to the aforementioned step S13 and the threshold voltage Vt of the next memory cell M (RA, CA) is verified. That is, when word line WL1 is selected in the aforementioned step S15, the threshold voltage Vt of a memory cell M10 positioned at the intersection of word line WL1 and bit line BL0 is verified.
In step S17, it is judged whether the column address CA is the final address CAMAX (=512) or higher. As a result, when the column address is the final address CAMAX or higher, the overerased cell detecting operation is terminated and processing returns to the erase operation shown in FIG. 3. On the other hand, when the column address is lower than the final address CAMAX, processing proceeds to step S18. In step S18, the column address CA is incremented. As a result, when bit line BL0 is selected in the aforementioned step S11, bit line BL1 is selected. Then, processing returns to the aforementioned step S12, and the row address RA is returned to the initial value xe2x80x9c0xe2x80x9d. Then, when bit line BL1 is selected in the aforementioned step S18, the threshold voltage Vt of a memory cell M01 positioned at the intersection of word line WL0 and bit line BL1 is verified.
Thus, every time the column address CA (=bit line BL number) is incremented by 1, a threshold voltage Vt of a memory cell M (RA, CA) is verified while the row address RA (=word line WL number) is successively incremented from xe2x80x9c0xe2x80x9d to xe2x80x9c1024xe2x80x9d. Then, when the threshold voltages Vt of all the memory cells become 0.5 V or higher as a result of verification of the threshold voltages Vt of all the memory cells in the block, the overerased cell detecting operation is terminated. On the other hand, when a threshold voltage Vt of a memory cell M (RA, CA) is 0.5 V or lower to determine an overerased state, processing proceeds to step S19.
In step S19, an initial value xe2x80x9c0xe2x80x9d is set in the number N of times a software program is performed. In step S20, a row address RA when an overerased state is determined in the step S14 is stored in a register Xadd. Subsequently, software program processing is started.
The reason why the row address RA of an overerased memory cell is stored in register Xadd is as follows. When it is determined that a memory cell M (RA, CA) is in an overerased state, there are first and second cases. In the first case, the threshold voltage of the memory cell M (RA, CA) lowers too rapidly depending on the variation of an erase characteristic. In the second case, a cell current flows even into an unselected state and hence the threshold voltage of the memory cell M (RA, CA) is apparently detected as low because there exists a memory cell M having a negative threshold voltage among other memory cells M (RA+1, CA) to M (1023, CA) which share a bit line BL with the memory cell M (RA, CA). Therefore, a software program needs to be successively repeated for memory cells M (RA, CA) to M (1023, CA) connected to the same bit line BL a predetermined number of times until their threshold voltages become 0.5 or higher. For this management, the row address RA of the memory cell M (RA, CA) is stored in register Xadd.
In step S21, a write pulse (program pulse) is applied to a memory cell M (RA, CA) to execute a software program for raising a threshold voltage Vt. In step S22, the threshold voltage Vt of the memory cell M (RA, CA) is verified. In step S23, as a result of the above verification, it is judged whether the threshold voltage Vt of the memory cell M (RA, CA) is higher than 0.5 V. As a result, when the threshold voltage is higher than 0.5 V, it is determined that the memory cell M (RA, CA) is not in an overerased state, and processing returns to the aforementioned step S15 to continue the overerased cell detection processing. On the other hand, when the threshold voltage is 0.5 V or lower, processing proceeds to step S24.
In step S24, since the threshold voltage Vt is still 0.5 V or lower even though the software program is executed for the memory cell M (RA, CA), the row address RA is incremented. In step S25, it is judged whether the row address RA is the final address RAMAX or higher. As a result, when the row address is the final address RAMAX or higher, processing proceeds to step S26, and when the row address is lower than the final address RAMAX, processing returns to the aforementioned step S21 and software program processing is performed for the next memory cell M (RA, CA).
Thus, while the row address RA (=word line WL number) is successively incremented from xe2x80x9cRAxe2x80x9d to xe2x80x9c1024xe2x80x9d, software program processing is executed for the memory cell M (RA, CA) until the threshold voltage Vt becomes higher than 0.5 V. For example, when the threshold voltage Vt does not become higher than 0.5 V even though a software program is executed after it is determined that a threshold voltage Vt of memory cell M00 connected to WL0 is 0.5 V or lower, the software program is executed for WL1. In this case as well, processing shifts to the next row address when the threshold voltage Vt is 0.5 V or less. This operation is repeated up to WL1023.
In step S26, XADD, which is the content stored in register Xadd, is set in the row address RA. In step S27, the number N of times the software program is executed is incremented. In step S28, it is judged whether the number N of times the software program is executed is xe2x80x9c10xe2x80x9d or more. As a result, when N is less than xe2x80x9c10xe2x80x9d, processing returns to the aforementioned step S21 and shifts to the next software program processing. On the other hand, when N is xe2x80x9c10xe2x80x9d or more, the erase operation is terminated as an erase failure.
That is, for example, when it is determined that the threshold voltage Vt of memory cell M00 connected to word line WL0 is 0.5 V or lower, the software program processing is repeated up to 10 times for memory cells M00 to M (1023, 0) until their threshold voltages Vt become higher than 0.5 V.
Hereafter, a verify method for detecting a memory cell M in an overerased state will be explained, which method is used in the aforementioned step S14 or S23 in the overerased cell detecting operation. The simplest method will be explained with reference to FIGS. 16-18.
Here, as shown in FIG. 18, apart from memory cells (main cell) M in a memory cell array where data is actually written or read, there is provided a memory cell for reference (reference cell) Mr which has the same characteristic as that of main cells M and is used for verifying threshold voltages Vt of these main cells M. Furthermore, the threshold voltage Vt of a selected main cell M in the memory cell array is determined by comparing a cell current Ir flowing into this reference cell Mr and a cell current Im flowing into the selected main cell M.
First, the threshold voltage Vt of the reference cell Mr is set as, for example, 3.0 V in advance. Consequently, an I-V characteristic of this reference cell Mr is as shown in FIG. 17, which indicates that, when 4.5 V is applied to word line WLref connected to the control gate of the reference cell Mr, the cell current Ir flows into the reference cell Mr.
Meanwhile, as shown in FIG. 16, when 2 V is applied to word line WLmain (one of WL0 to WL1023) connected to the control gate of a main cell M selected to verify the threshold voltage Vt, the current Im flows into the main cell M as a cell current.
Here, since the main cell M and the reference cell Mr are memory cells having the same I-V characteristic. Therefore, when the threshold voltage Vt of the main cell M is 0.5 V, the same cell current as that of the reference cell Mr flows by a gate voltage of 2.0 V which is obtained by 1.5 V (gate voltage 4.5 V of Mrxe2x88x92threshold voltage Vt 3.0 V of Mr)+0.5 V (the threshold voltage Vt of M). That is, Im=Ir is obtained. However, when the threshold voltage Vt of the main cell M is higher than 0.5 V, the cell current Im flowing into the main cell M becomes lower than the cell current Ir flowing into the reference cell Mr (Im less than Ir). On the contrary, when the threshold voltage Vt of the main cell M is lower than 0.5 V, the cell current Im becomes higher than the cell current Ir (Im greater than Ir). This is judged by a sense amplifier as shown in FIG. 18 to verify whether the cell is an overerased state.
That is, current values flowing into differential pairs in differential circuits constituting a sense amplifier change due to voltages generated in drains of the main cell M and the reference cell Mr by cell currents Im, Ir. Therefore, by comparing the amounts of the current values, it is judged whether the threshold voltage Vt of the main cell M is higher than a predetermined value (here, 0.5 V). That is, judgment is performed by current sense. In this case, an nMOS (metal oxide film semiconductor) transistor inserted between the differential pair and the ground potential becomes a constant current source, an operation point of the differential circuit is determined by a voltage bias inputted to the gate of the nMOS transistor.
The main cells M in the memory cell array are selected one by one and connected to the sense amplifier. Thereafter, 4.5 V is applied to the word line WLref of the reference cell Mr, while 2 V is applied to the word line WLmain of the selected main cell M. Thereby, it is successively verified whether the cell is in an overerased state.
However, the conventional verify method for detecting a memory cell M in an overerased state has the following problems. In the conventional overerase verify method, as described above, the main cells M are verified one by one. However, actually, 8 main cells M whose control gates are connected to one word line are verified in parallel. Since verify time of one block is expressed by (verify time of 1 memory cell M)xc3x97(number of memory cells in a block)/(number of cells processed in parallel), when 500 ns is required to verify one memory cell M, the verify time of one block in this case is
(500 nsxc3x97512xc3x971024)/8xe2x88x9233 ms. 
As shown in the algorithm of the overerased cell detecting operation shown in FIG. 15, this verify time is time required for a normal detection routine performed in steps S11 to S18 in FIG. 15. Therefore, when a memory cell M in an overerased state is detected and consequently a software program is executed, a software program time and verify time which the software program involves are further added to the verify time of 33 ms.
In an erase operation, as described above, erase-verify and erase pulse application are alternately repeated in erase-verify performed in the step S4 as shown in FIG. 3 so that threshold voltages of all memory cells M in a block become a predetermined voltage (3.0 V in FIG. 13) or lower. Furthermore, a variation in the erase characteristic of each memory cell M is not so actually wide as arises a problem. Therefore, in a normal condition, a memory cell in an overerased state rarely appears.
However, due to severe use environment of memory cells or a change thereof with time, a memory cell in an overerased state appears, so that a normal operation of a device cannot be performed. This allows no omittance of the algorithm for detection of an overerased cell and recovery of a threshold voltage in an erase operation so as to guarantee a normal operation of the device.
In addition, the overerase detection time needs to be shortened because it is supposed that high-speed erase whose erase time is, for example, 10 ms or less is required.
An object of the present invention is to provide a nonvolatile semiconductor memory device with which time of overerased cell detection essential for guarantee of reliability can be largely shortened in consideration to the present situation where an overerased cell rarely appears in a normal state.
An object of the present invention is to provide a method of detecting such an overerased cell as the above.
To achieve the above object, a first aspect of the present invention provides a nonvolatile semiconductor memory device comprising:
a memory cell array including:
a plurality of floating gate electric field effect transistors arranged in a matrix, each having a control gate, a drain and a source and being capable of electrically writing and erasing information, wherein a threshold voltage of each of the floating gate electric field effect transistors in a written state is higher than a threshold voltage of each of the floating gate electric field effect transistors in an erased state,
a plurality of row lines connected to control gates of the floating gate electric field effect transistors arranged in a row direction,
a plurality of column lines connected to drains of the floating gate electric field effect transistors arranged in a column direction, and
a common line commonly connected to sources of the floating gate electric field effect transistors constituting a block; and
a erase processing means which performs erase processing where, by controlling voltages applied to the row lines, the column lines and the common wiring,
firstly write before erase is performed,
secondly write-verify before erase is performed,
thirdly an erase pulse is applied,
fourthly verify after erase pulse application is performed,
fifthly first verify is performed to detect an overerased cell,
sixthly, when an overerased cell is detected in the first verify by applying a voltage to one of the row lines, second verify is performed to specify the overerased cell by applying a voltage different from the voltage applied in the first verify to the row line, and
seventhly, when the overerased cell is specified as a result of the second verify, write of a software program is performed for the overerased cell.
According to the above configuration, when erase processing is performed by the erase processing means, verify is performed after erase pulse application and then a first verify for detecting an overerased cell is performed. When an overerased cell is detected by this first verify, a second verify for specifying the overerased cell is performed. In this case, at the time of the second verify, a voltage different from the voltage applied to a row line at the time of the first verify is applied to the row line. Therefore, by lowering the voltage applied to the row line at the time of the first verify to the level of the threshold voltage in a floating gate electric field effect transistor to be an overerased cell, the first verify of a plurality of floating gate electric field effect transistors can be performed in a batch with low currents. On the other hand, by making the voltage applied to the row line at the time of the second verify higher than at the time of the first verify, detection sensitivity is increased and hence specific speed of the overerased cell can be increased.
Furthermore, in one embodiment of the present invention, the erase processing means has the first verify means which performs the first verify in units of the column lines by applying a voltage to all row lines connected to control gates of the plurality of floating gate electric field effect transistors whose drains are commonly connected to the column line so that one floating gate electric field effect transistor in an overerased state at most exists among the plurality of floating gate electric field effect transistors, and that a leakage current when the floating gate electric field effect transistor in an overerased state is unselected in a normal operation can be equal to a predetermined value or lower.
According to this embodiment, since the first verify is performed in units of the column lines, the number of times of verify is reduced in comparison with the case that the first verify is performed in units of individual floating gate electric field effect transistors. Therefore, the overerased cell detection time is shortened. At this time, the voltage applied to the row line is set so that there exists one floating gate electric field effect transistor in an overerased state at most, and that a leakage current when this floating gate electric field effect transistor in an overerased state is unselected is equal to a predetermined value or lower in a normal operation, and therefore, lower power consumption can be achieved.
A second aspect of the present invention provides a method of detecting an overerased cell in the nonvolatile semiconductor memory device according to the firs aspect of the invention, wherein
pass or failure is determined at time of the first verify and the second verify by comparing a current value of the column line connected to a drain of a reference cell and a current value of the column line connected to a drain of a target cell composed of a floating gate electric field effect transistor to be verified, the reference cell being composed of a floating gate electric field effect transistor which has the same structure as that of the aforementioned floating gate electric field effect transistor and is not written or erased.
According to the above configuration, the first verify and the second verify are performed by current sense using the reference cell. Therefore, a current value flowing into a target cell constituted by the floating gate electric field effect transistor to be verified can be directly detected. Therefore, for example, the first verify for a plurality of target cells whose drains are commonly connected to the column line can be performed in a batch.
Furthermore, in one embodiment of the present invention, the first verify and the second verify are performed by using the same reference cell.
According to this embodiment, the number of the reference cells is reduced to half, and expansion of the chip area is prevented. Furthermore, since current sense characteristics become the same at the time of the first verify and the second verify, there are less errors in detection of an overerased cell.
Furthermore, in one embodiment of the present invention, a first voltage is lower than a second voltage, a third voltage is lower than a fourth voltage, and the first voltage is lower than the third voltage, where
a voltage applied to a row line connected to a control gate of the target cell at time of the first verify is defined as the first voltage,
a voltage applied to a row line connected to a control gate of the reference cell at time of first verify is defined as the second voltage,
a voltage applied to the row line connected to the control gate of the target cell at time of the second verify is defined as the third voltage, and
a voltage applied to the row line connected to the control gate of the reference cell at time of the second verify is defined as the fourth voltage.
According to this embodiment, at the time of the first verify and second verify, the voltage applied to the row line on the reference cell side is higher than the voltage applied to the row line on the target cell side. Therefore, the state of the reference cell becomes stable, and detection accuracy is improved. Furthermore, the voltage applied to the row line on the target cell side at the time of the second verify is higher than the voltage applied to the row line on the target cell side at the time of the first verify. Therefore, sense sensitivity at the time of the second verify becomes higher than that of the first verify.
Furthermore, in one embodiment of the present invention, current values in the reference cell and the target cell are compared by a sense amplifier, and at time of the first verify, a predetermined voltage for detecting an overerased cell is applied to all the row lines in the block, while the column lines are successively selected and connected to the sense amplifier to detect the overerased cell in units of the column lines.
According to this embodiment, the first verify is performed in units of the column lines. Therefore, the number of times of verify is reduced in comparison with the case that the first verify is performed in units of individual floating gate electric field effect transistors, and hence the overerased cell detection time is shortened.
Furthermore, in one embodiment of the present invention, at time of the second verify, a voltage different from the voltage applied to the row lines at time of the first verify is successively applied to the row lines, and only a column line determined as including an overerased cell at time of the first verify is connected to the sense amplifier so as to specify the overerased cell in units of individual target cells.
According to this embodiment, the overerased cell is specified in units of individual target cells for a column line for which presence of an overerased cell is determined at the time of the first verify. Therefore, the overerased cell is precisely specified.
Furthermore, one embodiment of the present invention, the floating gate electric field effect transistor having a threshold voltage between 0 and 1 V inclusive in the memory cell array is detected as the overerased cell at time of the first verify and the second verify.
According to this embodiment, a floating gate electric field effect transistor having a threshold voltage between 0 V and 1 V inclusive is detected as the overerased cell. Therefore, the maximum value of a leakage current in a normal operation when detection omission occurs is restricted to the leakage current of a floating gate electric field effect transistor having a threshold voltage of 0 V. Furthermore, a small number of overerased cells positioned in the vicinity of the lower limit in distribution of threshold voltages of all the floating gate electric field effect transistors belonging to the memory cell array can be detected.
A third aspect of the invention provides a method of detecting an overerased cell in the nonvolatile semiconductor memory device according to the first aspect of the invention, wherein
pass or failure at time of the first verify is determined based on a voltage value of the column line connected to the drain of a target cell composed of a floating gate electric field effect transistor to be verified, and
pass or failure at time of the second verify is determined by comparing a current value of the column line connected to the drain of a reference cell and a current value of the column line connected to the drain of the target cell, the reference cell being composed of a floating gate electric field effect transistor which has the same structure as that of the aforementioned floating gate electric field effect transistor and is not written or erased.
According to the above configuration, the first verify is performed by voltage sense. Therefore, an overerased cell can be detected with favorable sensitivity in a short time.
Furthermore, in one embodiment of the present invention, a voltage between 0 and 1 V inclusive is applied to the row line connected to the control gate of the target cell at time of first verify.
According to this embodiment, a floating gate electric field effect transistor having a threshold voltage of between 0 V and 1 V inclusive is detected as the overerased cell. Therefore, the maximum value of a leakage current in a normal operation when detection omission occurs is restricted to the leakage current of a floating gate electric field effect transistor having a threshold voltage of 0 V. Furthermore, a small number of overerased cells positioned in the vicinity of the lower limit in distribution of threshold voltages of all the floating gate electric field effect transistors belonging to the memory cell array can be detected.
Furthermore, in one embodiment of the present invention, a voltage of a column line connected to the target cell is detected by a sense amplifier at time of the first verify, and a leakage current to be detected is controlled by controlling time when the column line connected to the drain of the target cell is connected to the sense amplifier.
According to this embodiment, by making time sufficiently long when the column line connected to the drain of the target cell is connected to the sense amplifier, a leakage current in a normal operation is sufficiently lowered.
Furthermore, in one embodiment of the present invention, a sixth voltage is lower than a seventh voltage, where
a voltage applied to a row line connected to the control gate of the target cell at time of the first verify is defined as a fifth voltage,
a voltage applied to the row line connected to the control gate of the target cell at time of second verify is defined as the sixth voltage, and
a voltage applied to a row line connected to the control gate of the reference cell at time of the second verify is defined as the seventh voltage.
According to this embodiment, the voltage applied to the row line on the reference cell side at the time of the second verify is higher than the voltage applied to the row line on the target cell side. Therefore, the state of the reference cell becomes stable, and detection precision is improved.
Furthermore, in one embodiment of the present invention, a voltage value of the column line connected to the target cell is detected by a first sense amplifier, and at time of the first verify, a predetermined voltage for detecting an overerased cell is applied to all the row lines in the block, and the column lines are successively selected to be connected to the first sense amplifier so as to detect the overerased cell in units of the column lines.
According to this embodiment, the first verify is performed in units of the column lines. Therefore, the number of times of verify is reduced in comparison with the case that the first verify is performed in units of individual floating gate electric field effect transistors, and therefore, the overerased cell detection time is shortened.
Furthermore, in one embodiment of the present invention, current values in the reference cell and the target cell are compared by a second sense amplifier at time of the second verify, and
at time of the second verify, a voltage different from the voltage applied to the row line at time of the first verify is successively applied at time of the second verify, and only column lines determined as including an overerased cell at time of the first verify are successively connected to the second sense amplifier so as to specify the overerased cells in units of individual target cells.
According to this embodiment, the overerased cell is specified in units of individual target cells for a column line in which presence of an overerased cell is determined at the time of the first verify. Therefore, the overerased cell is precisely specified.